oneChip
ATARI
This is my Atari FPGA page where I try
to track my progress (or lack of thereof) on my Atari 800 in a FPGA
project. If you want to know more contact me
directly.
News:
| 2003-05-01 |
Well I finally managed to get some
spare time devoted to this project.
After working with the latest
updates and constantly booting over the serial port I got tired
of this and decided to implement an SD card reader interface. In
the current implementation it only works in boot mode (Before
entering the Atari runtime mode) but the aim is to have it look
as disk D1. Now back to the computer to implement a simpe menu
system......
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| 2006-03-09 |
No real progress to report other
than I have cleaned up the code, removed all traces of
experimenting with SPI interfaces and other fun stuff :-) The
oneChipA now has an input signal (runMode) which determines
wether it should emulate an Atari 800 or Atari 5200. Oh, just
remembered I did implement the Pokey Serial Interface as well
and simulations seem fine. Just have to test in the real world.
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| 2006-02-16 |
After strugling with reflashing
the external program flash to many times i decided to go for a
system boot architecture where the system can boot the ATARI
BIOS (or any other program) either from the on board
configuration FLASH or a serial port.
I also did some restructuring
of the clock handling. So basically, the system now boots with
the 6502 running at 25MHz and downloads the BIOS from the
selected source (selectable with one of the slide switches) into
the system memory (on board SRAM). After this sequence, the
system selects an external 3.579545 MHz clock source for the
ATARI sub system and jumps to the reset vector. All of this is
accomplished by a program residing inside an internal FPGA ROM
block (really a pre initialized SRAM block). This way I can
easily select to download the ATARI BIOS (which I now have in
the configuration FLASH) or any program written for test
purposes over the serial port.
Well no progress on the real
ATARI stuff but extremly useful for debugging and testing.
O by the way, does anyone know
why it takes 15 minutes to extend a wavetable test bench in
ISE7.1i. It takes less than a few seconds to create a new file
with the desired size but extending the time of an existing
wavetable takes waaaaaay to long.
More to come soon.
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| 2006-02-06 |
This is the first
entry on this page so this is basically just a summary of the
current status.
To test and prototype the system I am using a Digilent Spartan-3
board with an XC3S400 device. To develop the VHDL model I am
using Xilinx ISE 7.1i with Modelsim.
The board I am using
At the moment I have managed to
implement a system with a 6502, a POKEY and a register model of
the ANTIC and GTIA. It is being fed from the outside by a FLASH
chip which basically is just a copy of the ROM's from a 800XL.
My first goal was to have
graphic mode 0 up and running so that the Basic screen would
show up on a monitor. I figured that would be a somewhat
realistic goal. Hehe, well realistic or not a few months later I
actually have it up and running. But this is pretty much what it
can do right now, no Player/Missile DMA and no other graphic
modes are available. But it is a good platform to continue
working from. I will try to take some pictures of my setup
later.
I will try to describe the system more closely later, just
haven't the time right now.
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Documentation:
These documents are just here for
reference and does probably not describe the current status of the
project. I'll try to keep them updated but if you really want the
latest you should probably contact me.
If you have any question you can always
contact me.
(C) Pontus Oldberg 2006
You can freely use any images, source code, text or other material from
this site as long as it is for a non- commercial purpose. If you want to
use something for any other purpose please contact me.
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